Why Binary Counters Fail Domain Crossings
Passing multi-bit signals between asynchronous clock domains without proper synchronization causes functional failures in silicon. A 4-bit binary counter count[3:0] operates in domain clk_A. The value of count is sampled directly by registers in an asynchronous domain clk_B without a FIFO or Gray code encoding. The counter transitions from decimal 7 (0111) to decimal 8 (1000). Evaluate the bit transitions and identify the intermediate states that clk_B might capture due to routing skew and setup/hold violations.
Constraints
count[3:0]is a standard binary counter.clk_Aandclk_Bare completely asynchronous with no phase relationship.- Routing skew means individual bits of the bus can arrive at the destination flip-flops at slightly different times.
Topics
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