Negative Edge-Triggered DFF: CLK Polarity Swap
High-speed double data rate (DDR) interfaces and specialized clock dividers require capturing data on both phases of a clock signal. The negative edge-triggered flip-flop samples its input when the clock transitions from high to low.
Implement a master-slave D flip-flop that captures input D on the falling edge of CLK.
| CLK transition | D | Q_next | |------------------|-----|----------| | Rising (0 to 1) | X | Q | | Falling (1 to 0) | 0 | 0 | | Falling (1 to 0) | 1 | 1 | | Static | X | Q |
Constraints
- Implement using a master-slave latch topology.
- Ensure the master latch is transparent when
CLKis high. - Ensure the slave latch is transparent when
CLKis low.
Topics
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