PAL Output Inversion Trick
Legacy Programmable Array Logic (PAL) devices have fixed OR-gate widths, strictly limiting the number of product terms per output. When a required logic function exceeds this physical limit, designers program the inverse function into the array and route it through the macrocell's inverting output buffer.
The required function Y = A | B | C | D requires four product terms in standard sum-of-products form. The target PAL macrocell only supports a maximum of three product terms per output. Implement this logic function by building its inverse and passing it through a final output inverter.
| A | B | C | D | Y | |-----|-----|-----|-----|-----| | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 0 | 1 | 1 | | 0 | 0 | 1 | 0 | 1 | | 0 | 0 | 1 | 1 | 1 | | 0 | 1 | 0 | 0 | 1 | | 0 | 1 | 0 | 1 | 1 | | 0 | 1 | 1 | 0 | 1 | | 0 | 1 | 1 | 1 | 1 | | 1 | 0 | 0 | 0 | 1 | | 1 | 0 | 0 | 1 | 1 | | 1 | 0 | 1 | 0 | 1 | | 1 | 0 | 1 | 1 | 1 | | 1 | 1 | 0 | 0 | 1 | | 1 | 1 | 0 | 1 | 1 | | 1 | 1 | 1 | 0 | 1 | | 1 | 1 | 1 | 1 | 1 |
Constraints
- Use only AND gates and NOT gates.
- Do not use OR gates or NOR gates.
- The final gate driving
Ymust be a NOT gate representing the macrocell output buffer.
Topics
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