Memory Word Width Expansion
Processors require specific data bus widths that rarely match the capacity of individual memory chips. Combining multiple narrow memory ICs in parallel creates a single wider memory bank.
Construct an 8-bit wide memory using two 4-bit wide RAM components. The system provides an 8-bit write data bus data_in, a 4-bit address bus addr, and a 1-bit write enable signal we. Route the lower 4 bits of data_in to the first RAM block and the upper 4 bits to the second RAM block. Both memory blocks must share the same we and addr signals. Concatenate their read outputs to form the 8-bit data_out bus.
Constraints
- Use exactly two 4-bit RAM components.
- Route
addrandweto both memory blocks simultaneously. - Split
data_inand mergedata_outwithout crossing bit orders.
Topics
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