PLA Shared Term Optimization
Programmable Logic Arrays rely on a programmable AND plane followed by a programmable OR plane to evaluate multiple boolean functions simultaneously. Silicon area scales directly with the number of product terms, making cross-function term sharing a critical physical design optimization.
Implement a Binary Coded Decimal (BCD) to Excess-3 converter. The circuit accepts a 4-bit BCD input A (MSB), B, C, D (LSB) and produces a 4-bit Excess-3 output W (MSB), X, Y, Z (LSB). Input combinations 1010 through 1111 will never occur in the system and serve as don't care conditions for logic minimization.
| A | B | C | D | W | X | Y | Z | |-----|-----|-----|-----|-----|-----|-----|-----| | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 |
Constraints
- Minimize the total number of unique product terms across all four outputs to simulate an optimal PLA AND-plane.
- Use only AND, OR, and NOT gates.
- Do not use XOR or XNOR gates.
Topics
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