Propagation Delay Asymmetry: Rising vs. Falling Output

MediumLogic CircuitTiming Diagram

A positive-edge-triggered D flip-flop updates its output Q on the rising edge of CLK with a high-transition delay (t_pcqH) of 3 time units and a low-transition delay (t_pcqL) of 5 time units.

Three signals are shown: CLK (clock, period 2), D (input data), and Q (output, initially 0).

Trace Q across all 16 time steps.

Constraints

Output Q only changes after a rising edge of CLK.
A 0-to-1 transition on Q takes exactly 3 time steps to appear after the clock edge.
A 1-to-0 transition on Q takes exactly 5 time steps to appear after the clock edge.
The value captured is strictly the value of D at the exact moment of the CLK rising edge.

Topics

timing-analysisflip-flopspropagation-delay

Solve this problem

Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Propagation Delay Asymmetry: Rising vs. Falling Output

MediumLogic CircuitTiming Diagram

A positive-edge-triggered D flip-flop updates its output Q on the rising edge of CLK with a high-transition delay (t_pcqH) of 3 time units and a low-transition delay (t_pcqL) of 5 time units.

Three signals are shown: CLK (clock, period 2), D (input data), and Q (output, initially 0).

Trace Q across all 16 time steps.

Constraints

Output Q only changes after a rising edge of CLK.
A 0-to-1 transition on Q takes exactly 3 time steps to appear after the clock edge.
A 1-to-0 transition on Q takes exactly 5 time steps to appear after the clock edge.
The value captured is strictly the value of D at the exact moment of the CLK rising edge.

Topics

timing-analysisflip-flopspropagation-delay

Solve this problem

Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Propagation Delay Asymmetry: Rising vs. Falling Output

Constraints

Topics

Solve this problem

Related problems

Propagation Delay Asymmetry: Rising vs. Falling Output

Constraints

Topics

Solve this problem

Related problems