Hold Constraint in Zero-Delay Path: Buffer Insertion
A zero-delay path between two positive-edge-triggered D flip-flops causes a hold violation that must be resolved by inserting a delay buffer. Five signals are shown: CLK (clock, period 2), IN (input to the first flip-flop), Q1 (output of the first flip-flop), Q2_unbuf (output of the second flip-flop without a buffer), and Q2_buf (output of the second flip-flop with a buffer). Because the propagation delay is shorter than the hold time, Q2_unbuf experiences a hold violation and incorrectly captures the newly updated value of Q1 on the same clock edge. The inserted buffer delays the signal enough to satisfy the hold time, allowing Q2_buf to correctly capture the previous value of Q1. Trace Q1, Q2_unbuf, and Q2_buf across all 8 time steps.
Constraints
- All flip-flop outputs initially start at 0.
Q2_unbufcaptures the new value ofQ1evaluated at the exact same rising edge due to the hold violation.Q2_bufcaptures the old value ofQ1present immediately before the rising edge.
Topics
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