Retiming: Moving a Register to Balance Pipeline Stages
To balance a critical path, a register initially placed after 12 units of combinational logic is retimed backward by 5 units. The logic is now split into two balanced 7-unit stages: Stage 1 computes A AND B, and Stage 2 computes Q_MID XOR C. Two positive-edge-triggered flip-flops are used: Q_MID captures the output of Stage 1, and OUT captures the output of Stage 2. Five signals are shown: CLK (clock, period 2), inputs A, B, C, and outputs Q_MID, OUT (both initially 0). Trace Q_MID and OUT across all 12 time steps.
Constraints
- Both
Q_MIDandOUTupdate strictly on the LOW-to-HIGH transitions ofCLK. OUTevaluatesQ_MID XOR Cusing the stable value ofQ_MIDpresent immediately before the clock edge.
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