Read After Write Hazard and Bypass Forwarding
Pipelined processors frequently encounter structural hazards when an instruction attempts to read a register in the exact clock cycle another instruction writes to it. Without intervention, the read operation fetches stale data. A bypass forwarding network solves this by routing the incoming write data directly to the output port when a simultaneous read and write target the same address.
Construct the bypass logic for a single read port. The circuit receives the data fetched from the storage array (reg_read_data), the incoming write data (write_data), the target read address (read_addr), the target write address (write_addr), and the write enable signal (write_en).
The output out_data must reflect the bypassed write_data if a valid write is occurring at the requested read address. In all other cases, it must output reg_read_data. Address inputs are 2 bits wide. Data buses are 4 bits wide.
Constraints
- Implement combinational bypass logic only.
- Do not include sequential register storage elements.
- Route the data using a single multiplexer.
Topics
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