Dual Read Port Multiplexing
Superscalar processors and modern ALUs require fetching multiple operands simultaneously from a shared register file. The read logic provides independent, asynchronous paths from the storage array to the execution units.
Route one of four 1-bit data registers (D0, D1, D2, D3) to Out1 based on the select lines S1_1 and S1_0. Simultaneously, route one of the same four registers to Out2 based on select lines S2_1 and S2_0. Both ports must be able to read the identical register at the exact same time without signal contention.
The routing behavior for each port follows this logic:
| S1_1 / S2_1 | S1_0 / S2_0 | Out1 / Out2 | |-----------------|-----------------|-----------------| | 0 | 0 | D0 | | 0 | 1 | D1 | | 1 | 0 | D2 | | 1 | 1 | D3 |
Constraints
- Implement using basic combinational logic gates or multiplexers.
- Do not use tri-state buffers to share a single output bus.
- Maintain strictly independent data paths for
Out1andOut2.
Topics
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