Register File Read Port Contention
Shared data buses in processor register files rely on strict access control to prevent catastrophic hardware failure. The schematic shows a 4-word register file driving a single shared read bus DATA_OUT. The read enable signals for the four registers, labeled RE0 through RE3, control tri-state buffers connected to the bus. These signals are driven by a custom address decoder receiving a 2-bit read address ADDR[1:0] and a global READ_EN signal. The decoder logic is defined as RE0 = READ_EN * ADDR[1]' * ADDR[0]', RE1 = READ_EN * ADDR[1]', RE2 = READ_EN * ADDR[1] * ADDR[0]', and RE3 = READ_EN * ADDR[1] * ADDR[0]. Analyze the decoder logic to find any flaws in the read port arbitration. Determine the specific input conditions that lead to bus collisions and evaluate the electrical consequences on DATA_OUT.
Constraints
- Assume all tri-state buffers are ideal and have infinite impedance when disabled.
- The system uses standard CMOS logic levels where a collision between opposite states results in an undefined voltage level.
ADDR[1]is the most significant bit of the address.
Topics
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