ROM Access Time and Critical Path
Read-only memory often forms the critical path in a synchronous system because large array structures possess significant parasitic capacitance. The circuit under analysis is a $2^N \times M$ asynchronous ROM block.
The critical path consists of an $N$-to-$2^N$ address decoder, a programmable OR plane representing the memory array, and an output buffer stage. The address inputs A[N-1:0] arrive at $t=0$. The decoder has a fixed propagation delay of 450 ps. The OR plane delay scales linearly with the number of wordlines: it takes 15 ps per row to drive the bitline capacitance. The output buffer adds a fixed 200 ps delay before the data outputs D[M-1:0] are valid.
Calculate the total read access time for different ROM sizes and identify the bottleneck in the datapath.
Constraints
- Total read access time is the sum of the decoder delay, the array delay, and the output buffer delay.
- The number of rows in the OR plane is determined by $2^N$, where
Nis the number of address bits. - Assume worst-case data patterns where the bitline must fully swing from precharge to ground.
Topics
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