Ring Counter: Asynchronous Preset for Power-On Initialization
Control state machines often require a valid initial state before the first clock edge arrives. A power-on reset sequence relies on asynchronous initialization to force the initial token into the correct flip-flop.
Construct a 4-bit ring counter that shifts a single high bit rightward on each rising edge of clk, wrapping from the least significant bit back to the most significant bit. The circuit must handle an active-low initialization signal PRE_bar. When PRE_bar is asserted low, the counter must immediately output 1000 without waiting for a clock transition.
| PRE_bar | Current Q3 Q2 Q1 Q0 | Next Q3 Q2 Q1 Q0 (after clk ↑) | |-----------|-----------------------------|------------------------------------------| | 0 | Any | 1000 (Immediate, ignores clk) | | 1 | 1000 | 0100 | | 1 | 0100 | 0010 | | 1 | 0010 | 0001 | | 1 | 0001 | 1000 |
Constraints
- Use standard D flip-flops for the state elements.
- The initialization must be purely asynchronous.
- Do not use synchronous reset logic to establish the power-on state.
Topics
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