Ring Counter: Initialization via Synchronous Load
Fully synchronous designs avoid asynchronous resets to prevent timing violations. A ring counter acting as a control state machine must initialize its one-hot sequence exactly at a clock edge rather than immediately upon a control signal assertion.
The circuit is a 4-bit ring counter with a synchronous LOAD signal. When LOAD is 1, the next rising clock edge forces the outputs Q3, Q2, Q1, and Q0 to the binary value 1000. When LOAD is 0, the next rising clock edge shifts the bits right, with Q0 feeding back into Q3.
| LOAD | Current Q3 | Current Q2 | Current Q1 | Current Q0 | Next Q3 | Next Q2 | Next Q1 | Next Q0 | |--------|--------------|--------------|--------------|--------------|-----------|-----------|-----------|-----------| | 1 | X | X | X | X | 1 | 0 | 0 | 0 | | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 |
Constraints
- Use exactly four D flip-flops for state storage.
- Do not use the asynchronous preset or clear pins on the flip-flops.
- Use 2:1 multiplexers on the D inputs to select between the fixed initialization value and the ring counter feedback.
Topics
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