ROM as a Universal Logic Element
Look-up tables in FPGAs are essentially small read-only memories that evaluate combinational logic by mapping inputs directly to stored output values.
The schematic provided shows a 4-input combinational logic circuit with inputs A, B, C, and D driving a single output Y. The circuit implements the boolean function Y = (A XOR B) + (C AND D'). A 16x1 ROM is proposed to replace this entire gate-level implementation. The ROM address lines A3, A2, A1, and A0 are connected to inputs A, B, C, and D respectively.
Determine the exact binary contents required in the ROM to perfectly replicate the behavior of the original circuit. Evaluate the address mapping and identify the stored bits at specific memory locations.
Constraints
- Address line mapping strictly follows the order
A3=A,A2=B,A1=C,A0=D. - Memory addresses are evaluated in standard hexadecimal from
0x0to0xF. - ROM contents are strictly single bit values:
0or1.
Topics
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