Sequence Counter Partial Specification
Communication protocols and interleaved memory controllers often operate on partial timing specifications where valid data points occur only at specific intervals. The sequence generator must provide a 10-state cycle where the even-cycle states are strictly defined as 0, 2, 4, 6, and 8.
To minimize combinational logic overhead and standardize the interface, resolve the unspecified odd-cycle states by bridging the gaps with standard sequential integers: 1, 3, 5, 7, and 9. The resulting circuit operates as a standard mod-10 (BCD) counter. When rst is high, the counter must reset to 0.
| Cycle Type | Cycle Index | Q (Decimal) | Q (Binary) | |------------|-------------|---------------|--------------| | Reset | N/A | 0 | 0000 | | Even | 0 | 0 | 0000 | | Odd | 1 | 1 | 0001 | | Even | 2 | 2 | 0010 | | Odd | 3 | 3 | 0011 | | Even | 4 | 4 | 0100 | | Odd | 5 | 5 | 0101 | | Even | 6 | 6 | 0110 | | Odd | 7 | 7 | 0111 | | Even | 8 | 8 | 1000 | | Odd | 9 | 9 | 1001 | | Even | 10 | 0 | 0000 |
Constraints
- Implement a synchronous 4-bit counter that wraps from 9 (1001) back to 0 (0000).
- Use a synchronous active-high reset
rstto force the state to 0. - Unused states (10 through 15) must not lock up the counter.
Topics
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