Serial Link with Start and Stop Bits
Asynchronous serial communication relies on framing to determine byte boundaries without a shared clock. The universal asynchronous receiver-transmitter (UART) protocol prepends a start bit and appends a stop bit to every transmitted data byte.
The transmitter must capture an 8-bit parallel input and shift it out serially at a rate of one bit per clock cycle. The output frame must consist of 10 bits: a logical 0 start bit, the 8 data bits transmitted least-significant bit (LSB) first, and a logical 1 stop bit.
When load is 1, the circuit captures data_in and holds tx_out at 1 (the idle state). When load transitions to 0, the circuit begins transmission. The first cycle outputs the 0 start bit. The next 8 cycles output the data bits. The 10th cycle outputs the 1 stop bit. The output remains 1 until the next load assertion.
Constraints
- Use sequential logic elements to construct the shift register and frame counter.
- The
tx_outsignal must default to 1 during reset, idle, and load states. - The transmission sequence must begin exactly one clock cycle after
loadtransitions to 0.
Topics
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