SIPO: Serial-to-Parallel Conversion Timing
A 100kHz serial link transmits a 7-bit character to a 7-bit Serial-In Parallel-Out (SIPO) shift register. The shift register captures SER_IN into Q0 on every LOW-to-HIGH transition of CLK and shifts existing bits toward Q6. A separate output register captures the shift register bits on the LOW-to-HIGH transition of STROBE. All outputs are initially 0.
Six signals are shown: CLK (clock, period 2), SER_IN (serial data input), STROBE (active-HIGH latch clock), and outputs Q0, Q6, and LATCH_Q6.
Trace Q0, Q6, and LATCH_Q6 across all 16 time steps.
Constraints
- All flip-flops and registers are positive-edge-triggered.
- Assume zero propagation delay. Outputs update exactly at the time step of the clock edge.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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