Simple 4-Bit Serial Link: PISO to SIPO
Serial links like SPI, I2C, and PCIe serialize parallel data for transmission across limited physical wires and reconstruct it at the receiver. The PISO to SIPO chain forms the fundamental atomic model of all serial digital communication.
When load is 1, the transmitter captures the 4-bit parallel input D. When load is 0, the transmitter shifts this data out serially, one bit per clk cycle, to the receiver. After exactly four shift cycles, the receiver's 4-bit parallel output Q must exactly equal the original transmitted word.
Behavioral sequence for a single transmission: 1. Cycle 0: load = 1. PISO captures D. 2. Cycles 1-3: load = 0. PISO shifts data out serially over a single wire; SIPO shifts data in. 3. Cycle 4: load = 0. Final shift occurs. Q now equals the original D.
Constraints
- Construct both a 4-bit PISO and a 4-bit SIPO using D flip-flops, multiplexers, and basic logic gates.
- Connect the PISO and SIPO using exactly one serial data wire.
- Connect all flip-flops to the shared
clksignal. - Do not use pre-built shift register macros.
Topics
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