Start Bit Detection Waveform
A positive-edge-triggered UART receiver detects a LOW start bit on the serial line and shifts in 8 subsequent data bits before pulsing a valid signal.
Three signals are shown: CLK (clock, period 2), RX (serial input, idle HIGH), and STROBE (output, initially 0).
Trace STROBE across all 24 time steps.
Constraints
- The receiver evaluates inputs strictly on the LOW-to-HIGH transition of
CLK. - The start bit is detected on the first rising edge where
RXis sampled LOW. - The 8 data bits are sampled on the 8 rising edges immediately following start bit detection.
STROBEmust be asserted HIGH for exactly one clock cycle immediately after the 8th data bit is sampled.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.