Serial-to-Parallel with Double-Buffered Output
High-speed serial interfaces like SPI or UART require receiving continuous back-to-back byte streams without data loss. A double-buffered serial-to-parallel converter captures incoming bits in a shift register and transfers the complete byte to a holding register, giving the downstream logic a full eight clock cycles to read the data before it is overwritten.
The circuit receives a continuous serial bitstream on sin. On every clock cycle, sin is shifted into an internal 8-bit shift register. An internal modulo-8 counter tracks the incoming bits. On the 8th bit of every byte, the complete 8-bit word is loaded into an output register driving pout. The output register must hold this value stable for the next 8 clock cycles while the shift register receives the next byte. The rst signal synchronously resets the internal counter and clears all registers to zero.
| Cycle | rst | sin | pout | Description | |-------|-------|-------|--------|-------------| | 0 | 1 | 0 | 0 | Reset all registers | | 1 | 0 | Bit 7 | 0 | Shift in MSB of Byte 1 | | 2-7 | 0 | Bits | 0 | Shift in remaining bits | | 8 | 0 | Bit 0 | 0 | Shift in LSB of Byte 1 | | 9 | 0 | Bit 7 | Byte 1 | pout updates, shift MSB of Byte 2 | | 10-16 | 0 | Bits | Byte 1 | pout holds stable | | 17 | 0 | Bit 7 | Byte 2 | pout updates, shift MSB of Byte 3 |
Constraints
- Synchronous active-high reset on
rst. - Output
poutmust only update exactly every 8 clock cycles after reset. - The first received bit must become the most significant bit (MSB) of the 8-bit output.
Topics
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