SIPO: Continuous Stream
A positive-edge-triggered 3-bit shift register receives continuous serial DATA and shifts left (SR = {SR[1:0], DATA}) on every LOW-to-HIGH transition of CLK, while a synchronous parallel output register captures the shift register's state on the same clock edge only when STROBE is HIGH.
Five signals are shown: CLK (clock, period 2), DATA (serial input), STROBE (active-high capture enable), OUT2 (output register MSB, initially 0), and OUT0 (output register LSB, initially 0).
Trace OUT2 and OUT0 across all 16 time steps.
Constraints
- The output register captures the shift register state synchronously, meaning it evaluates the shift register's value immediately before the current clock edge applies its shift.
- The shift register shifts left: the oldest bit resides at the MSB (
OUT2) and the newest bit at the LSB (OUT0).
Topics
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