LFSR Serial CRC Generator
Serial communication protocols like Ethernet and USB rely on Cyclic Redundancy Checks (CRC) to detect frame errors. The transmitter computes a running checksum using a Linear Feedback Shift Register (LFSR) and appends it to the data: the receiver runs the exact same circuit on the incoming stream, and a final state of zero indicates an error-free transmission.
Implement a 4-bit CRC generator using a Galois LFSR. The circuit maintains a 4-bit state exposed on the crc_out port, representing Q[3:0].
State Update Rules: * crc_out initializes to 0000 when rst is high. * On each clock cycle, the intermediate feedback signal is evaluated as: fb = Q[3] ^ data_in * The next state Q_next is computed as: * Q_next[0] = fb * Q_next[1] = Q[0] ^ fb * Q_next[2] = Q[1] * Q_next[3] = Q[2]
*(Note: The ^ operator denotes logical XOR).*
Constraints
- Use only D flip-flops and basic combinational logic gates.
- The
rstsignal must be synchronous and active-high. - Maintain a single continuous 4-bit output for
crc_out.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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