Serial Link: Clock Inversion at Receiver Debug
A serial link receiver captures an incoming bit stream into an 8-bit shift register.
Expected behavior:
The receiver samples the DataIn signal on the rising edge of Clk and shifts it into DataOut. After 8 clock cycles, DataOut holds the complete transmitted byte.
High-speed validation tests are failing. When transmitting the byte 0xA5 (10100101), DataOut evaluates to 0x22. Low-speed tests and static patterns like 0xFF pass without error. The received byte is corrupted during short bit transitions. Inspect the circuit and correct the fault.
Constraints
- Modifying the clock distribution network is allowed.
- Adding new flip-flops or shift registers is prohibited.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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