Serial Shift Register as Echo Circuit
Delay lines are essential for signal alignment in multi-channel systems and time-domain reflectometry. Implementing a delay line as a digital shift register allows an incoming signal to be delayed by a precise, predictable number of clock cycles.
The circuit must implement an 8-stage Serial-In Serial-Out (SISO) shift register. A logic pulse applied to the serial input D_in must propagate through the register chain and appear at the final output Q7_out exactly 8 clock cycles later.
| Cycle | D_in | Q7_out | |-------|--------|----------| | 1 | 1 | 0 | | 2 | 0 | 0 | | 3 | 0 | 0 | | 4 | 0 | 0 | | 5 | 0 | 0 | | 6 | 0 | 0 | | 7 | 0 | 0 | | 8 | 0 | 1 | | 9 | 0 | 0 |
Constraints
- Implement an 8-stage serial-in, serial-out shift register.
- Use exactly 8 D flip-flops.
- Connect all flip-flops to a common clock signal.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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