UART-Style 10-Bit Frame: Full Transmit and Receive
Serial communication forms the backbone of embedded systems, with UART being the most ubiquitous protocol for device-to-device data exchange. A complete transceiver requires precise framing to serialize parallel data and recover it at the destination.
Implement a full UART-style transmitter and receiver operating at a 1-bit-per-clock baud rate.
Transmitter Behavior: When tx_start is asserted high, the transmitter captures the 8-bit tx_data input. Over the next 10 clock cycles, it shifts out a 10-bit frame on tx_out: a start bit (0), the 8 data bits (LSB first), and a stop bit (1). The tx_out line must remain in an idle high state (1) when not actively transmitting.
Receiver Behavior: The receiver continuously monitors the rx_in line for a falling edge, which indicates an incoming start bit. Once detected, it samples the next 8 bits into an internal register. On the 10th bit, it verifies the stop bit is high (1). If the stop bit is valid, it updates the 8-bit rx_data output with the received byte and asserts rx_valid high for exactly one clock cycle.
Constraints
- Implement synchronous logic using the rising edge of
clk. - Use an asynchronous active-high
rstto initialize all state, clearrx_datato0, and settx_outto1. - Do not use oversampling: process exactly one bit per clock cycle for both transmission and reception.
rx_datamust hold its previous value until a new, valid frame is completely received.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.