SPI Clock Generator
Every synchronous serial bus relies on a master clock to dictate timing across the interface. The SPI master generates the serial clock line to ensure reliable data sampling at the peripheral.
Derive the SPI clock output SCK from the high-speed system clock. To guarantee a perfect 50 percent duty cycle, use a toggle structure driven by an enable pulse en. On every rising edge of the system clock, if en is 1, SCK must invert its current state. If en is 0, SCK must hold its state. An active-high synchronous reset rst forces SCK to 0.
| rst | en | SCK (current) | SCK (next) | |-------|------|-----------------|--------------| | 1 | X | X | 0 | | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | | 0 | 1 | 0 | 1 | | 0 | 1 | 1 | 0 |
Constraints
- Implement using only rising-edge triggered flip-flops and standard combinational logic gates.
- Use a fully synchronous active-high reset.
- Do not gate the system clock line directly.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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