Break Condition Detector
Out-of-band signaling allows UART receivers to detect fatal errors or reset commands without relying on standard data frames. A break condition occurs when the transmission line is driven low for an extended duration that violates the standard protocol framing.
The circuit must monitor the rx line on each clock cycle. If rx remains at logic 0 for 12 consecutive clock cycles, assert break_flag to 1. If rx evaluates to logic 1 at any time, the internal count must reset and break_flag must immediately evaluate to 0. An active-high rst signal synchronously clears the internal state.
Constraints
- Use synchronous logic.
- The
rstsignal must be synchronous and active-high. - The internal counter must not overflow and clear
break_flagifrxremains 0 indefinitely.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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