Overrun Error Detector

HardLogic CircuitBuild

Serial communication interfaces drop data if the host processor fails to service the receive buffer in time. The overrun error detector flags this condition to prevent silent data corruption.

The circuit tracks the availability of unread data using a data_valid register and catches missed reads using an overrun_err register. The behavior follows these exact rules:

When rx_done asserts, data_valid goes high.
When read_ack asserts, data_valid goes low.
If rx_done asserts while data_valid is already high and read_ack is low, overrun_err goes high.
The overrun_err flag is sticky: once asserted, it remains high until a reset occurs.
If rx_done and read_ack assert on the same clock cycle, data_valid remains high and no overrun occurs.
rst is a synchronous active-high reset that clears both registers.

Constraints

Implement synchronous active-high reset logic.
Use only D flip-flops for state elements.
Do not use latches.

Topics

RegistersInterfaceError Handling

Solve this problem

Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Overrun Error Detector

HardLogic CircuitBuild

Serial communication interfaces drop data if the host processor fails to service the receive buffer in time. The overrun error detector flags this condition to prevent silent data corruption.

The circuit tracks the availability of unread data using a data_valid register and catches missed reads using an overrun_err register. The behavior follows these exact rules:

When rx_done asserts, data_valid goes high.
When read_ack asserts, data_valid goes low.
If rx_done asserts while data_valid is already high and read_ack is low, overrun_err goes high.
The overrun_err flag is sticky: once asserted, it remains high until a reset occurs.
If rx_done and read_ack assert on the same clock cycle, data_valid remains high and no overrun occurs.
rst is a synchronous active-high reset that clears both registers.

Constraints

Implement synchronous active-high reset logic.
Use only D flip-flops for state elements.
Do not use latches.

Topics

RegistersInterfaceError Handling

Solve this problem

Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Overrun Error Detector

Constraints

Topics

Solve this problem

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Overrun Error Detector

Constraints

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