Full UART Transmitter
Microcontrollers require asynchronous serial interfaces to transmit data to peripherals without locking up the main execution thread. This circuit serializes an 8-bit parallel data word into a standard UART frame consisting of a start bit, 8 data bits, and a stop bit.
The module receives an 8-bit data_in payload and a tx_start pulse. When rst is high, the system remains in an idle state where tx_out is 1 and tx_ready is 1. Upon detecting a high tx_start signal while idle, the module latches data_in and begins transmission on the next clock cycle. During the active transmission sequence, tx_ready must remain 0.
The transmission sequence on tx_out must be exactly 10 cycles long: 1. One clock cycle driven to 0 representing the start bit. 2. Eight clock cycles shifting out the latched data_in, least significant bit (LSB) first. 3. One clock cycle driven to 1 representing the stop bit.
Once the stop bit cycle completes, tx_ready must return to 1 to indicate the transmitter can accept a new payload.
Constraints
- Implement as a synchronous digital circuit using D flip-flops.
- Latch the input data at the start of transmission to prevent corruption if
data_inchanges mid-frame. - Ignore the
tx_startsignal entirely while a transmission is already in progress.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.