SPI Mode 1 Timing
Many high-speed sensors require SPI communication where data is shifted on the leading clock edge and sampled on the trailing edge. This specific phase and polarity configuration ensures setup and hold times are met across long bus traces.
Implement the core datapath for an SPI Mode 1 interface. The system uses a clock signal sck which idles low. The mosi output must update with the value of tx_bit on the rising edge of sck. The rx_bit output must capture the value of miso on the falling edge of sck. An active-high rst signal asynchronously clears both outputs to 0.
| Event | mosi | rx_bit | |-------|--------|----------| | rst = 1 | 0 | 0 | | sck ↑ | tx_bit | Unchanged | | sck ↓ | Unchanged | miso |
Constraints
- Use D flip-flops for state retention.
- Do not use transparent latches.
- The reset signal must clear the state asynchronously.
Topics
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