SPI Mode 2 Timing
Peripheral sensors and display drivers often dictate strict communication timing requirements. In SPI Mode 2, the clock idles high, requiring precise inverted-edge logic to coordinate data transfer between the controller and the target device.
Construct the 1-bit physical layer interface for a Mode 2 SPI controller. The sck signal idles high. The transmitted data tx_data must be driven onto mosi on the rising edge of sck. The received data miso must be captured into rx_data on the falling edge of sck.
| Event | Action | |-------|--------| | sck ↓ | Capture miso into rx_data | | sck ↑ | Update mosi from tx_data |
Constraints
- Use only D flip-flops and basic combinational logic gates.
- Do not use latches.
- Route
mosiandrx_datadirectly from flip-flop outputs.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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