Synchronous Reset Released at Same Edge as Data
A positive-edge-triggered D flip-flop with an active-low synchronous reset captures D at every LOW-to-HIGH transition of CLK if RST_bar is 1, and clears to 0 if RST_bar is 0.
Four signals are shown: CLK (clock, period 2), RST_bar (active-low synchronous reset), D (data input), and Q (output, initially 0).
Trace the output signal Q across all 10 time steps.
Constraints
- Output
Qonly changes state at the LOW-to-HIGH transition ofCLK. - Synchronous reset
RST_baris evaluated exactly at the rising clock edge. - If a signal transitions at the exact time step of the clock edge, the new value is the one evaluated by the flip-flop.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.