Synchronous Reset Wired to Asynchronous Path Debug
A synchronous reset flip-flop updates its state only on the active clock edge, ensuring predictable cycle-level timing.
Expected behavior:
The Q output must track the D input on the rising edge of CLK. When RST is high, Q must transition to 0 only on the next rising edge of CLK.
Simulation shows Q clearing immediately mid-cycle when RST asserts, regardless of the CLK state. The reset is behaving asynchronously. Inspect the circuit and correct the fault.
Constraints
- Do not add new logic gates.
- The circuit must implement a strictly synchronous reset.
- Modify only the existing wiring to correct the fault.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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