DFF with Synchronous Set and Reset: Priority-Encoded D Path
Register-file designs and arithmetic unit controllers frequently require state elements that can be forced high or low on a clock edge. When multiple control signals can fire simultaneously, the datapath requires explicit priority encoding to ensure deterministic behavior.
Construct a D flip-flop with a synchronous reset signal R and a synchronous set signal S. The reset condition has strict priority over the set condition. All state updates occur on the rising edge of the clock.
| R | S | D | Next Q | |-----|-----|-----|----------| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | | 0 | 1 | 0 | 1 | | 0 | 1 | 1 | 1 | | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | | 1 | 1 | 0 | 0 | | 1 | 1 | 1 | 0 |
Constraints
- Implement the priority logic strictly in the combinational path feeding the flip-flop's
Dinput. - Use exactly one standard D flip-flop.
- Do not use asynchronous set or clear pins on the flip-flop.
Topics
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