Synchronous Reset Priority
A positive-edge-triggered D flip-flop with a synchronous active-low reset evaluates its inputs at every LOW-to-HIGH transition of CLK. Four signals are shown: CLK (clock, period 2), RST_n (synchronous active-low reset), D (data input), and Q (output, initially 0). Trace Q across all 12 time steps.
Constraints
- The output
Qonly changes state in response to a LOW-to-HIGH transition onCLK. - Synchronous reset
RST_nhas strict priority over dataD. - If
RST_nis 0 at the rising clock edge,Qis forced to 0 regardless of the value ofD.
Topics
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