UART Transmitter Data Shifter
Asynchronous serial communication requires holding data bits stable for an entire baud period so the receiver can reliably sample them. The transmission shift register serializes a parallel payload and advances precisely when commanded by the baud rate generator.
When load is high, the register captures the 8-bit data_in. While load is low, the register shifts out one bit to tx_out every time baud_tick asserts, starting with the least significant bit (LSB). When baud_tick is low, tx_out must remain stable. Upon synchronous rst, tx_out must default to 1 to match the standard UART idle state.
Constraints
- Implement using sequential and combinational logic.
- Shift data out LSB first.
- Update the shift register state only when
baud_tickis high orloadis high. - Drive
tx_outdirectly from the least significant bit of your internal shift register.
Topics
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