UART Transmitter Stop Bit
Every asynchronous serial link must guarantee a minimum recovery time between frames. The UART stop bit returns the line to the idle state, ensuring the receiver can reliably detect the next start bit.
The circuit uses a baud clock (clk) and an active-high synchronous reset (rst). When data_done is high for one cycle, the circuit must assert tx_stop_bit high on the next clock cycle. If tx_req is high while tx_stop_bit is active, the circuit must assert start_next high on the following clock cycle to immediately begin a new frame. If tx_req is low during the stop bit, start_next must remain low.
Constraints
- Trigger all sequential logic on the rising edge of
clk. - Implement an active-high synchronous reset using
rst. - Register all outputs to prevent combinational glitches on the interface.
Topics
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