Zero Insertion Serializer
Serial communication protocols like CAN and USB require frequent edge transitions for reliable clock recovery. A bit stuffing circuit monitors the outgoing data stream and automatically injects dummy bits to break up long sequences of identical values.
The circuit tracks the number of consecutive 1s transmitted. During normal operation, dout mirrors din. When three consecutive 1s are transmitted, the circuit enters an insertion cycle. During the insertion cycle, dout is forced to 0 and stall is asserted to 1 to signal the upstream data source to hold its current bit. The internal counter resets after any 0 is transmitted.
| rst | din | Current Count | dout | stall | Next Count | |-------|-------|---------------|--------|---------|------------| | 1 | X | X | 0 | 0 | 0 | | 0 | 0 | 0 | 0 | 0 | 0 | | 0 | 1 | 0 | 1 | 0 | 1 | | 0 | 0 | 1 | 0 | 0 | 0 | | 0 | 1 | 1 | 1 | 0 | 2 | | 0 | 0 | 2 | 0 | 0 | 0 | | 0 | 1 | 2 | 1 | 0 | 3 | | 0 | X | 3 | 0 | 1 | 0 |
Constraints
- Implement synchronous reset using the
rstsignal. - Use D flip-flops to maintain the consecutive bit count.
- The
stallsignal must assert exactly during the cycle the stuffed0is output.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.