Zero Deletion Deserializer
Serial communication protocols like USB and CAN use bit stuffing to maintain clock synchronization. The receiver must strip out these dummy bits to recover the original data payload.
The circuit receives a continuous serial bitstream on din. It shifts valid bits into an 8-bit parallel register dout, shifting new bits into the LSB and existing bits left. If three consecutive valid 1s are shifted in, the protocol dictates that the immediately following bit is a stuffed bit. The circuit must ignore this stuffed bit: it must not be shifted into dout. After ignoring the stuffed bit, the consecutive 1s counter resets to 0.
| Cycle | rst | din | dout | Note | |-------|-------|-------|--------|------| | 1 | 1 | 0 | 0 | Reset | | 2 | 0 | 1 | 1 | Valid | | 3 | 0 | 1 | 3 | Valid | | 4 | 0 | 1 | 7 | Valid (3rd consecutive 1) | | 5 | 0 | 0 | 7 | Stuffed bit is ignored | | 6 | 0 | 0 | 14 | Valid, shifted in normally |
Constraints
- Use a synchronous active-high reset
rst. doutmust initialize to 0.- Shift new valid bits into the LSB of
dout. - The stuffed bit must not affect the consecutive
1s counter.
Topics
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