Manchester Encoder
Baseband communication systems like Ethernet and RFID embed clock and data on a single wire to ensure synchronization. The encoder accomplishes this by guaranteeing a voltage transition in the middle of every bit period.
Construct a Manchester encoder driven by a double-speed system clock. The data input remains stable for a full bit period, which equals two clock cycles. A logic 1 is encoded as a high-to-low transition. A logic 0 is encoded as a low-to-high transition.
Use an internal phase state that tracks the current half of the bit period. When rst is 1, the phase resets to 0. When rst is 0, the phase toggles on every clock cycle. The output tx must follow this precise behavior based on data and phase:
| data | phase | tx | |--------|---------|------| | 0 | 0 | 0 | | 0 | 1 | 1 | | 1 | 0 | 1 | | 1 | 1 | 0 |
Constraints
- Implement an internal 1-bit phase register that toggles every clock cycle.
- Reset the phase register to 0 synchronously when
rstis high. - Generate the output
txcombinationally using onlydataand the internal phase.
Topics
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