Simplified Manchester Decoder
Ethernet and RFID systems embed clock signals directly into data streams to prevent receiver drift. The decoder must recover the original bit sequence from these continuous transitions.
A 4x oversampling clock drives the circuit. The sync input pulses high for one cycle to mark the 0 percent start of a new bit period. The mid-bit transition occurs at the 50 percent mark. To safely recover the data and ignore edge jitter, sample the man_in stream at the 75 percent mark, which is exactly three cycles after the sync pulse.
During the 75 percent mark cycle, output the sampled bit on data_out and assert valid to 1. At all other times, valid and data_out must be 0.
Constraints
- Use a synchronous reset driven by
rst. validmust strictly pulse for one clock cycle per bit period.data_outmust be forced to 0 whenvalidis 0.- Do not use negative-edge triggered flip-flops.
Topics
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