Baud Rate Generator
Asynchronous serial interfaces like UART require a precise local timebase to sample incoming data correctly. A baud rate generator derives this slow enable tick from a much faster system clock.
Implement a modulo-16 counter that acts as a baud tick generator. The circuit takes a synchronous active-high reset rst. The internal 4-bit counter must increment on every active clock edge. When the internal counter reaches 15, the output tick must assert high for exactly one clock cycle. On the following cycle, the counter must wrap around to 0. When rst is high, the internal counter resets to 0 and tick must be 0.
Constraints
- Implement using sequential and combinational logic elements.
- Do not use a gated clock for the output:
tickmust be a synchronous single-cycle enable signal. - The reset signal
rstmust be synchronous and active-high.
Topics
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