Start Bit Edge Detector
Asynchronous serial protocols like UART idle high and rely on a falling edge to signal the beginning of a new data frame. Detecting this initial transition is critical to clear the baud rate generator and align the receiver timing perfectly with the incoming transmission.
The circuit must monitor the rx line and output a single-cycle high pulse on detect immediately upon sensing a high-to-low transition. Assume all inputs are synchronized to the clock.
| Cycle | rx | detect | |-------|------|----------| | 1 | 1 | 0 | | 2 | 1 | 0 | | 3 | 0 | 1 | | 4 | 0 | 0 | | 5 | 1 | 0 | | 6 | 0 | 1 |
Constraints
- Design must be fully synchronous.
- The
detectsignal must remain high for exactly one clock cycle per falling edge. - Assume all internal flip-flops initialize to zero.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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