Start Bit Validation
Asynchronous serial receivers must distinguish true data transmissions from transient line noise. A short electromagnetic glitch on the receive line can cause a falling edge, which a naive receiver might misinterpret as a start bit, leading to framing errors and garbage data.
The state machine monitors the rx line for a falling edge (a synchronous transition from 1 to 0) while in the idle state. When a 0 is sampled, it waits for exactly 2 additional clock cycles. On the 3rd clock cycle after the initial 0 was sampled, it checks the rx line again.
If rx is 0 on this 3rd cycle, it is a valid start bit: assert start_detected to 1 for that single clock cycle, then return to the idle state.
If rx is 1 on this 3rd cycle, the initial edge was a noise spike: abort the sequence, keep start_detected at 0, and return immediately to the idle state to wait for the next falling edge.
Constraints
- Implement as a synchronous finite state machine.
- Use a synchronous, active-high
rstsignal to initialize the state machine to the idle state. start_detectedmust be high for exactly one clock cycle per valid start bit.- The machine must return to the idle state immediately after the 3rd cycle check, regardless of the
rxvalue.
Topics
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