Topic

Verilog

Writing synthesizable Verilog: modules, always blocks, blocking and nonblocking assignments, and the mistakes that only show up in simulation.

1 post · Practice problems

  • Verilog

    Blocking vs nonblocking assignments in Verilog

    When to use = and when to use <= in Verilog: what each assignment does, why mixing them breaks a shift register, and the rules that prevent simulation races.

    · 5 min read