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Codiode/Problems/Sequential Logic

Johnson vs. Ring Counter: Period and State Comparison

MediumLogic CircuitTiming Diagram

A 4-bit shift register forms a Ring counter when its last bit Q3 feeds back directly to Q0, and a Johnson counter when the inverted last bit feeds back to Q0.

Three signals are shown: CLK (clock, period 2), QR0 (Ring counter output bit 0), and QJ0 (Johnson counter output bit 0). Both circuits are positive-edge-triggered and shift right from Q0 to Q3. The Ring counter begins in state 1000 (meaning QR0 is initially 1 and all other bits are 0), while the Johnson counter begins in state 0000.

Trace QR0 and QJ0 across all 16 time steps.

Constraints

  • Both shift registers evaluate the value at Q3 immediately prior to the rising clock edge to determine the next value of Q0.
  • Output transitions occur only on the LOW-to-HIGH edge of CLK.
  • State shifts strictly from index 0 toward index 3.

Topics

CountersState MachinesShift Registers

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